1. Field of the Invention
The invention relates to an all digital phase locked loop (ADPLL) and, in particular, to a fractional spur reduction technique for an ADPLL.
2. Description of the Related Art
All digital phase locked loops (ADPLLs) have been reported to have superior performance with low cost. However, a fraction-N operation of an ADPLL induces high fractional spur as compared to a conventional charge pump-based fraction-N PLL, which is the most popular architecture used in wireless applications.
In a conventional delta-sigma fractional PLL, the fractional spur is induced by non-linearity of the loop such as charge pump current mismatch and clock feed-through. However, the induced fractional spur can be suppressed to zero by a passive low pass filter to make circuit design more robust. On the other hand, for an all-digital PLL (ADPLL) as shown in FIG. 1, non-linearity of the loop is induced by quantization errors/non-linearity/meta-stability of a time to digital converter (TDC) and a digital controlled oscillator (DCO). The spur induced by the non-linearity can not be filtered to zero by a digital low pass filter or a digital algorithm because the resolution of the digital loop filter is finite, which is limited by the quantization errors of the DCO. As a result, the fractional spurs exist in an ADPLL. Accordingly, if a DCO's quantization errors can be reduced, the resolution of the digital loop filter will be closer to that of an analog loop filter. Thus, the digital low pass filter and the digital algorithm would effectively be able to eliminate spurs.
To improve a DCO's resolution, a frequency dithering technique is recommended to obtain a higher resolution average frequency. Although the noise induced by the quantization error is reduced using this technique, this technique cannot eliminate the fractional spur. This is because the short-term DCO quantization error remains the output signal. This transient quantization error will be sampled into the loop and amplified by gain variation of the TDC. Additionally, it is impossible to achieve a low DCO quantization error since the required MOS capacitor geometry will be smaller than what an advanced process can provide.
FIG. 1 is a block diagram of a conventional TDC-based fractional-N ADPLL. The TDC converts phase error into a digital domain and then a digital loop filter processes that digital data. The output of the digital loop filter is transferred into a time domain by the DCO. Since quantization error of the output is determined by resolution of the DCO, not by the digital loop filter, a digital modulator is required to improve the average frequency resolution of the DCO.
FIG. 2 (FIGS. 2A and 2B) is a functional block diagram of a conventional DCO used in the conventional TDC-based fractional-N ADPLL shown in FIG. 1. The switching capacitor array in this DCO is used to digitally control the frequency of the LC oscillator. The capacitor array is separated into an integer part and a fractional part with the output signal device size. In order to eliminate non-monotonic DCO gain induced by device mismatch between the integer and fractional bits, the dynamic element match (DEM) technique is used. A high speed dithering signal generated by the SDM modulates the unit capacitor to achieve a higher DCO average frequency resolution, as shown in FIG. 3. The desired high resolution is achieved by toggling the DCO between frequencies f1 and f1+Δf. The frequency resolution with long-term average is smaller than the quantization error Δf, but the short-term quantization error still equals to Δf.